The present invention relates generally to an array of flash electrically erasable programmable read only memory (EEPROM) cells and, in particular, to an architecture for an array of flash EEPROM cells with source side injection.
A xe2x80x9cflashxe2x80x9d type electrically erasable programmable read only memory (EEPROM) includes a plurality of memory cells each of which includes a floating gate in a field effect transistor structure. The floating gate is positioned over but insulated from a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate, but is also insulated therefrom. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage (threshold) that must be applied to the control gate before the transistor is turned xe2x80x9conxe2x80x9d to permit conduction between its source and drain regions is controlled by the level of charge on the floating gate. A transistor is programmed to one of two states by accelerating electrons from the substrate channel region, through a thin gate dielectric and onto the floating gate.
The state of the memory cell transistor is read by placing an operating voltage across its source and drain and on its control gate, and then detecting the level of current flowing between the source and drain as to whether the device is programmed to be xe2x80x9conxe2x80x9d or xe2x80x9coffxe2x80x9d at the control gate voltage selected. A specific, single cell in a two-dimensional array of EEPROM cells is addressed for reading by application of a source-drain voltage to source and drain lines in a column containing the cell being addressed, and application of a control gate voltage to the control gates in a row containing the cell being addressed.
Current trends are directed towards the desirability of providing flash EEPROMs with increased storage capacity and reduced substrate size. While the benefits of scaling are suitable to a certain extent, problems can arise as the size of the EEPROM memory cells is further reduced. For example, short channel effects begin to adversely impact operation of the memory cells. In addition, high programming currents may become necessary.
In view of the aforementioned shortcomings associated with conventional flash EEPROMs, there is a strong need in the art for a flash EEPROM memory cell array which allows for continued scaling. More specifically, there is a strong need in the art for an array which provides for increased memory cell density while avoiding short channel effects and/or the need for high programming currents.
According to the present invention, a flash EEPROM array is provided which has a unique split gate architecture. Such architecture provides for high density arrangement of the memory cells using source side injection. The split gate array architecture of the present invention is particularly well suited for continued scaling with current flash processing technology.
In accordance with one particular aspect of the present invention, a flash electrically erasable programmable read only memory (EEPROM) is provided. The EEPROM includes a plurality of flash memory cells formed on a semiconductor substrate, the plurality of memory cells being arranged in a matrix of m rows and n columns, wherein the memory cells in each column are connected in series and include a drain coupled to a common bit line. In addition, the EEPROM includes a plurality of trenches formed in the semiconductor substrate, each of the plurality of trenches being formed between a corresponding pair of the n columns of memory cells. Moreover, the EEPROM includes a plurality of transistors formed at least in part in a corresponding sidewall of the plurality of trenches, each of the plurality of transistors connecting a source of a corresponding one of the memory cells to a Vss supply voltage.
According to another aspect of the invention, a method is provided for making a flash EEPROM. The method includes the step of forming a plurality of flash memory cells formed on a semiconductor substrate, the plurality of memory cells being arranged in a matrix of m rows and n columns, wherein the memory cells in each column are connected in parallel and include a drain coupled to a common bit line. The method further includes the steps of forming a plurality of trenches in the semiconductor substrate, each of the plurality of trenches being formed between a corresponding pair of the n columns of memory cells; and forming a plurality of transistors at least in part in a corresponding sidewall of the plurality of trenches, each of the plurality of transistors connecting a source of a corresponding one of the memory cells to a Vss supply voltage.
In accordance with still another aspect of the invention, a method is provided for forming an EEPROM. The method includes the steps of forming a plurality of trenches in a semiconductor substrate; doping the bottom of each of the trenches with a dopant; filling the trenches with a trench isolation material; forming a plurality of flash memory cells formed on the semiconductor substrate, the plurality of memory cells being arranged in a matrix of m rows and n columns separated by the plurality of trenches, wherein the memory cells in each column are connected in series and include a drain coupled to a common bit line; forming a plurality of word lines each extending along a corresponding row of the memory cells which are operative to select simultaneously each of the memory cells in the corresponding row; removing portions of the trench isolation material by a self aligned etch using the word lines as a mask to expose the bottom and sidewalls of the trenches in regions between adjacent word lines; forming an oxide layer on the exposed bottom and sidewalls of the trenches at least in the regions between the adjacent word lines; and forming a plurality of control lines each extending between and parallel to a corresponding pair of the word lines, the control lines each being operative to control the conductivity of transistors connected between the memory cells and a Vss supply voltage which are formed by a source of the connected memory cell, the doped bottom of a corresponding trench, and a channel therebetween formed in the sidewall of the corresponding trench.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.